1. Field of the Invention
The invention relates to an architecture for a scan-based integrated circuit (IC). More specifically, the invention relates to a method and circuitry to reduce cycle time in shifting data between an external interface and through a combinational decompressor and/or compressor of a combinational scan compression circuit.
2. Related Art
FIG. 1A illustrates a flow 10 of prior art, for processing a scan test pattern. In flow 10, step 11 sets up the scan chain configuration using flip-flops in the design, thereby identifying the scan cells of the scan chain. Step 12 shifts the scan-in values into the active scan chains. Step 13 exits the scan configuration. Step 14 applies stimulus to the inputs of the logic to be tested (such as logic 101 in FIG. 1B), and measures the outputs. Step 15 pulses the clocks to capture the logic's response in the flip-flops. Step 16 sets up the scan chain configuration. Step 17 shifts the scan-out values from the active scan chains. Step 18 exits the scan configuration.
For clarification of various steps discussed above, FIG. 1B illustrates a prior art electronic device which includes a circuit 100 that implements combinational scan compression (CSC). Accordingly, CSC circuit 100 includes a combinational decompressor 110, a combinational compressor 120, and a number of scan chains 101A-101Z coupled between combinational decompressor 110 and combinational compressor 120. Combinational decompressor 110 typically includes a number of multiplexers as shown in FIG. 1C (or exclusive OR gates). Similarly, combinational compressor 120 typically includes a number of exclusive OR gates as illustrated in FIG. 1D.
Referring back to FIG. 1B, CSC circuit 100 also includes a logic 101 to implement various features of functionality to be performed by the electronic device. Logic 101 typically includes a number of flip-flops that are required to implement the functionality. A subset of these same flip-flops are used, with multiplexers, to form scan cells that are organized into scan chains of the type shown in FIG. 1B. Specifically, flip-flops 101A1F and 101APF illustrated in FIG. 1E are portions of logic 101 that are made accessible via an external interface formed by input terminals 111A-111N, 112 and output terminals 121A-121Q of the electronic device, by use of multiplexers 101A1M and 101APM. Each corresponding pair, constituting a multiplexer driving a flip flop, forms a scan cell as shown in FIG. 1E.
Note that the primary input terminals 102PI and the primary output terminals 102PO of the logic 101 are physically identical to above-described input terminals 111A-111N, 112 and output terminals 121A-121Q of the external interface, but are shown separately in FIG. 1B to clearly show a distinction between scan mode operation and normal functional operation of CSC circuit 100. The difference between the two modes of operation is identified to CSC circuit 100 from an external source, via a scan enable signal on input terminal 112.
In FIG. 1A's step 11 multiplexers 101A1M and 101APM are added between logic 101 and flip-flops 123. Using a scan_enable (i.e. a control) signal, multiplexers 101A1M and 101APM can be configured to allow scan-in values to be shifted into flip-flops 101A1F and 101APF without going through logic 101 in step 102. In step 103, multiplexers 101A1M and 101APM can be reconfigured to accept values from logic 101. At this point, stimulus can be applied to CSC circuit 100 in step 104. A pulse can be applied to the clock CLK terminals of flip-flops 101A1F and 101APF to capture the resulting values in step 105. In step 106, multiplexers 101A1M and 101APM can be reconfigured to shift those resulting values out through the scan chain comprising flip-flops 123. Step 108 marks the end of processing a single scan test pattern.
The inventors of the current patent application note that the time required for a signal to propagate from an input terminal 111A to first scan cell 101A1F, through combinational decompressor 110 can be significant. This time along path 191, can easily impose a limit on the speed at which input data can be shifted into CSC circuit 100, if the delay between adjacent flip-flops in a scan chain is small. A similar delay limits the speed at which output data can be shifted from CSC circuit 100 along path 192 to an output terminal 121A. The inventors further note that scan chains 101A-101Z in CSC circuit 100 (FIG. 1B) are typically located far apart from terminals in external interface 111A-111N, 112 and 121A-121Q, relative to the distance between adjacent scan cells of any scan chain. Such distant location of scan chains from the external interface results in long wires and large wire delays in prior art circuits. Hence, the inventors believe that there is a need to overcome such large wire delays.